1. Field of the Invention
This invention relates to digital-to-analog converters of the type having a number of transistor current sources connected to an R-2R ladder network to develop binary-weighted currents. More particularly, this invention relates to such converters provided with means to minimize errors resulting from offset voltages in the transistor current sources.
2. Description of the Prior Art
One commonly used digital-to-analog converter, described in U.S. Pat. No. Re. 28,633 (Pastoriza), comprises separate transistor current sources connected in a common base configuration with the emitters coupled to a resistance network to develop binary-weighted bit currents through the transistors. The areas of the transistor emitters are proportioned to the corresponding bit currents to provide for equal current densities in the transistors, thereby producing equal emitter voltages which track with changes in temperature. By use of a reference transistor feedback arrangement, the bit currents all can be stabilized against changes in temperature, thereby substantially avoiding temperature errors in the output analog current.
Although the scaled-emitter area arrangement described above is effective in avoiding errors due to offset voltages, it does require relatively large amounts of IC chip area, particularly when used in high-resolution single-chip converters. To avoid that result, a different solution to the problem is presented in U.S. Pat. No. 3,940,760 (Brokaw). There, the current sources are matched transistors, i.e. having equal emitter areas, so that the V.sub.BE offset voltages do not track with temperature . The transistor bases are interconnected by respective resistors, and a current proportional to absolute temperature (PTAT) is caused to flow through all of those interbase resistors in series. This current produces temperature-responsive interbase compensating voltages which match the .DELTA.V.sub.BE voltages between successive current source transistors. Thus the emitters of all of the current source transistors are maintained at equal potential, so that there is no temperature-induced change in the bit currents through the current-setting resistance network resulting from offset voltage changes.
The interbase resistor arrangement described above is effective in minimizing errors due to differences in current-source V.sub.BE, and has gone into extensive commercial use. However, that arrangement does require the addition of a set of well-matched resistors and associated circuitry. Thus, it has been desired to provide offset voltage compensation in a more efficient manner.